Sabanci University Microelectronics Workshop


Advances in uncooled micro-bolometers



The high level of accumulated expertise by ULIS and CEA/LETI on uncooled microbolometers made from amorphous silicon enables ULIS to develop uncooled infrared focal plane array (IRFPA) with 17 μm pixel-pitch to enable the development of small power, small weight and power and high performance IR systems. Key characteristics of amorphous silicon based uncooled IR detector is described to highlight the advantage of this technology for system operation. A full range of products from 160 x 120 to 1024 x 768 has been developed. We will focus the presentation on the ¼ VGA with 17 μm pixel pitch. Readout integrated circuit (ROIC) architecture is described highlighting innovations that are widely on-chip implemented to enable an easier operation by the user. The detector configuration
(Integration time, windowing, gain, scanning direction), is driven by a standard I²C link. Like most of the visible arrays, the detector adopts the HSYNC/VSYNC free-run mode of operation driven with only one master clock (MC) supplied to the ROIC which feeds back pixel, line and frame synchronisation. On-chip PROM memory for customer operational condition storage is available for detector characteristics. Low power consumption has been taken into account and less than 60 mW is possible in analogue mode at 60 Hz. A wide electrical dynamic range (2.4V) is maintained despite the use of advanced CMOS node. The specific appeal of this unit lies in the high uniformity and easy operation it provides. The reduction of the pixel-pitch turns this TEC-less ¼ VGA array into a product well suited for high resolution and compact systems, including space applications. Noise equivalent temperature difference (NETD) of 35 mK and thermal time constant of 10 ms have been measured leading to 350 figure of merit. We insist on NETD tradeoff with wide thermal dynamic range, as well as the high characteristics uniformity and pixel operability, achieved thanks to the mastering of the amorphous silicon technology coupled with the ROIC design. This technology node associated with advanced packaging technique, paves the way to compact low power system.

Dr. Christel-Loic Tisse, ULIS